MM74HC76 - Dual J-K Flip-Flops with Preset and Clear

Product Overview

National

Datasheet Details

Part number	MM74HC76
Manufacturer	National
File Size	136.21 KB
Description	Dual J-K Flip-Flops with Preset and Clear
Datasheet	MM74HC76 Datasheet
Additional preview pages of the MM74HC76 datasheet.

Product details

Description

These high speed (30 MHz minimum) J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve the low power consumption and high noise immunity of standard CMOS integrated circuits along with the ability to drive 10 LS-TTL loads Each flip-flop has independent J K PRESET CLEAR and CLOCK inputs and Q and Q outputs These devices are edge sensitive to the clock input and change state on the negative going transition of the clock pulse Clear and preset are independent of the clock and acc

Features

Y Y Y Y Y Typical propagation delay 16 ns Wide operating voltage range Low input current 1 mA maximum Low quiescent current 40 mA maximum (74HC Series) High output drive 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package Truth Table Inputs PR L H L H H H H H CLR H L L H H H H H CLK X X X J X X X L H L H X L X X X L L H H X Outputs Q Q v v v v H H L L H L L Q0 Q0 H L L H TOGGLE Q0 Q0 This is an unstable condition and is not guaranteed TL F 5074.
1 Top View Order.

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Published: May 9, 2005 |