5476 Datasheet | National Semiconductor

Description This device contains two independent positive pulse triggered J-K flip-flops with plementary outputs The J and K data is processed by the flip-flop after a plete clock pulse While the clock is low the slave is isolated from the master On the positive transition of the clock the data from the J and K inputs is transferred to the master While the clock is high the J and K inputs are disabled On the negative transition of the clock the data from the master is trans- ferred to the slave The logic state of J and K inputs must not be allowed to change while the clock is high The data is transfered to the outputs on the falling edge of the clock pulse A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs Features Y Alternate Military Aerospace device (5476) is available Contact a National Semiconductor Sales Office Distributor for specifications Connection Diagram Function Table Dual-In-Line Package TL F 6528 - 1 Order Number 5476DMQB 5476FMQB DM5476J DM5476W or DM7476N See NS Package Number J16A N16E or W16A Inputs Outputs PR CLR CLK J K LH HL LL HH HH HH HH X XX L LL HL Q0 H Q0 L Toggle H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level e Positive pulse data The J and K inputs must be held constant while the clock is high Data is transfered to the outputs on the falling edge of the clock pulse e This configuration is nonstable that is it will not persist when the preset and or clear inputs return to their inactive (high) level Q0 e The output logic level before the indicated input conditions were established Toggle e Each output changes to the plement of its previous level on each plete active high level clock...