54AC646 Datasheet | National Semiconductor

Description The ’AC646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling functions available are illustrated in Figures 1, 2, 3, 4. n n n n n n Multiplexed real-time and stored data transfers TRI-STATE outputs 300 mil slim dual-in-line package Outputs source/sink 24 m A ’ACT646 has TTL patible inputs Standard Microcircuit Drawing (SMD) - ’AC646: 5962-89682 Features n Independent registers for A and B buses Logic Symbols Pin Names A0- A7 B0- B7 CPAB, CPBA SAB, SBA G DS100231-1 Description Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input IEEE/IEC DS100231-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100231 .national. Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100231-3 DS100231-4 Real Time Transfer A-Bus to B-Bus Storage from Bus to Register DS100231-9 DS100231-7 FIGURE 1. Real Time Transfer B-Bus to A-Bus FIGURE 3. Transfer from Register to Bus DS100231-10 DS100231-8 FIGURE 4. FIGURE 2. .national. Function Table Inputs G DIR H H H L L L L L L L L X X X H H H H L L L L CPAB H or L Data I/O (Note 1) SAB SBA X X X L L H H X X X X X X X X X X X L L H H Output Input Input Output Input Input A0- A7 B0- B7 Isolation Function CPBA H or L X Clock An Data into A Register Clock Bn Data into B Register An to Bn - Real Time (Transparent Mode) Clock An Data into A Register A Register to Bn (Stored...