54ACT825 Datasheet | National Semiconductor

Description .. The ’ACT825 is an 8-bit buffered register. They have Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included are multiple enables that allow multi-use control of the interface. The ’ACT825 has noninverting outputs and is fully patible with AMD’s Am29825. Features n n n n Outputs source/sink 24 m A Inputs and outputs are on opposite sides ’ACT825 has TTL-patible inputs Standard Microcircuit Drawing (SMD) - ’ACT825: 5962-91611 Logic Symbols IEEE/IEC DS100254-1 DS100254-3 Pin Names D0- D7 O0- O7 OE1, OE2, OE3 EN CLR CP Description Data Inputs Data Outputs Output Enables Clock Enable Clear Clock Input FACT™ is a trademark of Fairchild Semiconductor. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1999 National Semiconductor Corporation DS100254 .national. Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC .. DS100254-4 DS100254-2 Functional Description The ’ACT825 consists of eight D-type edge-triggered flip-flops. These devices have TRI-STATE ® outputs for bus systems, organized in a broadside pinning. In addition to the clock and output enable pins, the buffered clock (CP) and buffered Output Enable (OE) are mon to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE1, OE2 and OE3 LOW, the contents of the flip-flops are available at the outputs. When one of OE1, OE2 or OE3 is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ’ACT825 has Clear (CLR) and Clock Enable (EN) pins. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the...