54F14 Datasheet | National Semiconductor

Description The ’F14 contains six logic inverters which accept standard TTL input signals and provide standard TTL output levels They are capable of transforming slowly changing input signals into sharply defined jitter-free output signals In addition they have a greater noise margin than conventional inverters Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totempole output The Schmitt trigger uses positive feed back to effectively speed-up slow input transition and provide different input threshold voltages for positive and negative-going transitions This hysteresis between the positive-going and negative-going input thresholds (typically 800 m V) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations Features Guaranteed 4000V minimum ESD protection Standard Military Drawing 5962-88752 mercial 74F14PC Military Package Number N14A Package Description 14-Lead (0 300 Wide) Molded Dual-In-Line 14-Lead Ceramic Dual-In-Line 14-Lead (0 150 Wide) Molded Small Outline JEDEC 14-Lead (0 300 Wide) Molded Small Outline EIAJ 14-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F14DM (Note 2) 74F14SC (Note 1) 74F14SJ (Note 1) 54F14FM (Note 2) 54F14LM (Note 2) J14A M14A M14D W14B E20A Note 1 Devices also available in 13 reel Use Suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbol IEEE IEC Connection Diagrams Pin Assignment DIP SOIC and Flatpak Pin Assignment for LCC .. TL F 9461 - 1 TL F 9461 - 2 TL F 9461- 3 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9461 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 50 33 3 Input IIH IIL Output IOH IOL 20 m A b0 6 m A b 1 m A 20 m A In On Input Output Function Table Input A L...