54F192 Datasheet | National Semiconductor

Description The ’F192 is an up down BCD decade (8421) counter Separate Count Up and Count Down Clocks are used and in either counting mode the circuits operate synchronously The outputs change state synchronously with the LOW-to HIGH transitions on the clock inputs Separate Terminal Count Up and Terminal Count Down outputs are used as the clocks for a subsequent stage without extra logic thus simplifying multistage counter designs Individual preset inputs allow the circuit to be used as a programmable counter Both the Parallel Load (PL) and the Master Reset (MR) inputs asynchronously override the clocks Features Guaranteed 4000V minimum ESD protection mercial 74F192PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F192DM (Note 2) 74F192SC (Note 1) 74F192SJ (Note 1) 54F192FM (Note 2) 54F192LM (Note 2) J16A M16A M16D W16A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9496- 3 IEEE IEC TL F 9496 - 1 TL F 9496 - 2 TL F 9496- 6 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9496 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL Input IIH IIL HIGH LOW Output IOH IOL 10 30 10 30 10 10 10 10 10 10 50 33 3 50 33 3 50 33 3 20 m A b1 8 m A 20 m A b1 8 m A 20 m A b0 6 m A 20 m A b0 6 m A 20 m A b0 6 m A b 1 m A 20 m A b 1 m A 20 m A b 1 m A 20 m A CPU CPD MR PL P0 - P3 Q0 - Q3 TCD TCU Count Up Clock Input (Active Rising Edge) Count Down Clock Input (Active Rising Edge) Asynchronous Master Reset Input (Active HIGH)...