54F273 Datasheet | National Semiconductor

Description The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The state of each D input one setup time before the LOW-to-HIGH clock transition is transferred to the corresponding flip-flop’s Q output All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input The device is useful for applications where the true output only is required and the Clock and Master Reset are mon to all storage elements Features Y Ideal buffer for MOS microprocessor or memory Y Eight edge-triggered D flip-flops Y Buffered mon clock Y Buffered asynchronous Master Reset Y See ’F377 for clock enable version Y See ’F373 for transparent latch version Y See ’F374 for TRI-STATE version Y Guaranteed 4000V minimum ESD protection mercial 74F273PC 74F273SC (Note 1) 74F273SJ (Note 1) Military 54F273DM (Note 2) 54F273FM (Note 2) 54F273LM (Note 2) Package Number N20A J20A M20B M20D W20A E20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC TL F 9511 - 3 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9511 TL F 9511 - 5 RRD-B30M75 Printed in U S A Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC Obsolete Unit Loading Fan Out TL F 9511- 1 54F 74F Pin Names Description U L Input IIH IIL HIGH LOW Output IOH IOL D0 - D7 MR CP Q0 - Q7 Data Inputs Master Reset (Active...