54F573 Datasheet | National Semiconductor

Description The ’F573 is a high speed octal latch with buffered mon Latch Enable (LE) and buffered mon Output Enable (OE) inputs This device is functionally identical to the ’F373 but has different pinouts Features Y Y Y Y Y Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors Functionally identical to ’F373 TRI-STATE outputs for bus interfacing Guaranteed 4000V minimum ESD protection mercial 74F573PC Military Package Number N20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpak 20-Lead Ceramic Leadless Chip Carrier Type C 54F573DM (Note 2) 74F573SC (Note 1) 74F573SJ (Note 1) 54F573FM (Note 2) 54F573LM (Note 2) J20A M20B M20D W20A E20A Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9566- 1 IEEE IEC TL F 9566 - 3 TL F 9566 - 2 TL F 9566- 4 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9566 RRD-B30M115 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 150 40(33 3) Input IIH IIL Output IOH IOL 20 m A b0 6 m A 20 m A b0 6 m A 20 m A b0 6 m A b 3 m A 24 m A (20 m A) D 0 - D7 LE OE O0 - O7 Data Inputs Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs Functional Description The ’F573 contains eight D-type latches with 3-state output buffers When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When...