54LS114 Datasheet | National Semiconductor

Description The ’LS114 features individual J K and set inputs and mon clock and mon clear inputs When the clock goes HIGH the inputs are enabled and data will be accepted The logic level of the J and K inputs may be allowed to change when the Clock Pulse is HIGH and the bistable will perform according to the truth table as long as the minimum setup times are observed Input data is transferred to the outputs on the negative-going edge of the clock pulse Connection Diagram Dual-In-Line Package Logic Symbol TL F 10176 - 1 Order Number 54LS114DMQB 54LS114FMQB or 54LS114LMQB See NS Package Number E20A J14A or W14B VCC e Pin 14 GND e Pin 7 Pin Names J1 J2 K1 K2 CP CD SD1 SD2 Q1 Q2 Q1 Q2 Description Data Inputs Clock Pulse Input (Active Falling Edge) Direct Clear Input (Active LOW) Direct Set...