74F563 Datasheet | National Semiconductor

Description The ’F563 is a high-speed octal latch with buffered mon Latch Enable (LE) and buffered mon Output Enable (OE) inputs This device is functionally identical to the ’F573 but has inverted outputs Features Y Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Y Useful as input or output port for microprocessors Y Functionally identical to ’F573 mercial 74F563PC 74F563SC (Note 1) 74F563SJ (Note 1) Military 54F563DM (Note 2) 54F563FM (Note 2) 54F563LM (Note 2) Package Number N20A J20A M20B M20D W20A E20A Package Description 20-Lead (0 300 Wide) Molded Dual-In-Line 20-Lead Ceramic Dual-In-Line 20-Lead (0 300 Wide) Molded Small Outline JEDEC 20-Lead (0 300 Wide) Molded Small Outline EIAJ 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C Note 1 Devices also available in 13 reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC Obsolete TL F 9562 - 3 Unit Loading Fan Out Pin Names D0 - D7 LE OE O0 - O7 Description Data Inputs Latch Enable Input (Active HIGH) TRI-STATE Output Enable Input (Active LOW) TRI-STATE Latch Outputs 54F 74F UL HIGH LOW 10 10 10 10 10 10 150 40 (33 3) Input IIH IIL Output IOH IOL 20 m A b0 6 m A 20 m A b0 6 m A 20 m A b0 6 m A b3 m A 24 m A (20 m A) TL F 9562 - 5 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9562 RRD-B30M75 Printed in U S A Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9562- 1 Functional Description The ’F563 contains eight D-type latches with TRI-STATE output buffers When the Latch Enable (LE) input is HIGH data on the Dn inputs enters the latches In this condition the latches are transparent i e a latch output will change state each time its D input changes When LE is LOW the latches store the information that was present on the D inputs a setup...