74LVT16652 Datasheet | National Semiconductor

Description The LVT16652 consists of sixteen bus transceiver circuits with D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers Each byte has separate control inputs which can be shorted together for full 16-bit operation Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to HIGH logic level Output Enable pins (OEAB OEBA) are provided to control the transceiver function The transceivers are designed for low-voltage (3 3V) VCC applications but with the capability to provide a TTL interface to a 5V environment The LVT16652 is fabricated with an advanced Bi CMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation Features Input and output interface capability to systems at 5V VCC Bus-Hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion extraction permitted Power Up Down high impedance provides glitch-free bus loading Outputs source sink b32 m A a 64 m A Available in SSOP and TSSOP Functionally patible with the 74 series 16652 Latch-up performance exceeds 500 m A Connection Diagram Pin Assignment for SSOP and TSSOP Pin Names A0 - A16 B0 - B16 CPABn CPBAn SABn SBAn OEABn OEBAn Description Data Register A Inputs TRI-STATE Outputs Data Register B Inputs TRI-STATE Outputs Clock Pulse Inputs Select Inputs Output Enable Inputs SSOP EIAJ Order Number NS Package Number 74LVT16652MEA 74LVT16652MEAX MS56A TSSOP JEDEC 74LVT16652MTD 74LVT16652MTDX MTD56 TL F 12024 - 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1996 National Semiconductor Corporation TL F 12024 RRD-B30M17 Printed in U S A http national Logic Diagrams TL F 12024 - 2 TL F 12024 - 3 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation...