ADC081000 Datasheet | National Semiconductor

Description The ADC081000 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 1.6 GSPS. Consuming a typical 1.4 Watts at 1 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential parator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 500 MHz input signal and a 1 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are pliant with IEEE 1596.3-1996, with the exception of a reduced mon mode voltage of 0.8V. The converter has a 1:2 demultiplexer that feeds two LVDS buses, reducing the output data rate on each bus to half the sampling rate. The data on these buses are interleaved in time to provide a 500 MHz output rate per bus and a bined output rate of 1 GSPS. The converter typically consumes less than 10 m W in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the industrial (-40°C ≤ TA ≤ +85°C) temperature range. Features - - - - - Internal Sample-and-Hold Single +1.9V ±0.1V Operation Adjustable Output Levels Guaranteed No Missing Codes Low Power Standby Mode Key Specifications - - - - - - - Resolution Max Conversion Rate ENOB @ 500 MHz Input DNL Conversion Latency Power Consumption - Operating - Power Down Mode 8 Bits 1 GSPS (min) 7.5 Bits (typ) ±0.25 LSB (typ) 7 and 8 Clock Cycles 1.45 W (typ) 9 m W (typ) Applications - - - - - Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes munications Systems Test Instrumentation Block Diagram © 2009 National Semiconductor Corporation .national. Ordering Information Extended...