ADC081500 Datasheet | National Semiconductor

Description The ADC081500 is a low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sample rates up to 1.7 GSPS. Consuming a typical 1.2 W at 1.5 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential parator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.3 ENOB with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18 B.E.R. Output formatting is offset binary and the LVDS digital outputs are pliant with IEEE 1596.3-1996, with the exception of an adjustable mon mode voltage between 0.8V and 1.2V. The converter output has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to one-half the sample rate. The converter typically consumes less than 3.5 m W in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40˚C ≤ TA ≤ +85˚C) temperature range. Features n n n n n n n n Internal Sample-and-Hold Single +1.9V ± 0.1V Operation Choice of SDR or DDR output clocking Multiple ADC Synchronization Capability Guaranteed No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock Key Specifications n n n n n n Resolution Max Conversion Rate Bit Error Rate ENOB @ 748 MHz Input DNL Power Consumption - Operating - Power Down Mode 8 Bits 1.5 GSPS (min) 10-18 (typ) 7.3 Bits (typ) ± 0.15 LSB (typ) 1.2 W (typ) 3.5 m W (typ) Applications n n n n n Direct RF Down Conversion Digital Oscilloscopes Satellite Set-top boxes munications Systems Test Instrumentation Block Diagram © 2005 National Semiconductor Corporation DS201531...