ADC082500 Datasheet | National Semiconductor

Description Note: This product is currently in development. - ALL specifications are design targets and are subject to change. The ADC082500 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 3.4 GSPS. Consuming a typical 1.8 Watts at 2.5 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential parator design, the innovative design of the internal sample-andhold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters up to Nyquist, producing a high 7.0 ENOB with a 748 MHz input Signal. A 2.5 GHz sample rate will provide a 10-18 B.E.R. The ADC082500 achieves a 2.5GSPS sampling rate by utilizing both the rising and falling edge of a 1.25 GSPS input clock. Output formatting is offset binary and the LVDS digital outputs are pliant with IEEE 1596.3-1996, with the exception of an adjustable mon mode voltage between 0.8V and 1.2V. The ADC has a 1:4 demultiplexer that feeds four LVDS buses and reduces the output data rate on each bus to a quarter of the sampling rate. The ADC can be programmed into the 1:2 Output Mode where the data is output on the Dc and Dd channels at the rate of the input clock. The converter typically consumes less than 20 m W in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial (-40˚C ≤ TA ≤ +85˚C) temperature range. Features n n n n n n n n n n Internal Sample-and-Hold Single +1.9V ± 0.1V Operation Choice of SDR or DDR output clocking 1:2 or 1:4 Selectable Output Demux Clock Phase Adjust for Multiple ADC Synchronization Guaranteed No Missing Codes Serial Interface for Extended Control Fine Adjustment of Input Full-Scale Range and Offset Duty Cycle Corrected Sample Clock Test pattern Key Specifications n n...