ADC11DS105 Datasheet | National Semiconductor

Description The ADC11DS105is a high-performance CMOS analog-todigital converters capable of converting two analog input signals into 11-bit digital words at rates up to 105 Mega Samples Per Second (MSPS). The digital outputs are serialized and provided on differential LVDS signal pairs. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external ponent count, while providing excellent dynamic performance. The ADC11DS105 may be operated from a single +3.0 or +3.3V power supply. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs accept a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC11DS105 can be operated with an external 1.2V reference. The selectable duty cycle stabilizer maintains performance over a wide range of clock duty cycles. A serial interface allows access to the internal registers for full control of the ADC11DS105's functionality. The ADC11DS105 is available in a 60-lead LLP package and operates over the industrial temperature range of - 40°C to +85°C. Features - - - - - - Clock Duty Cycle Stabilizer Single +3.0 or +3.3V supply operation Serial LVDS Outputs Serial Control Inteface Overrange Outputs 60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch) Key Specifications - - - - - - Resolution Conversion Rate SNR (f IN = 240 MHz) SFDR (f IN = 240 MHz) Full Power Bandwidth Power Consumption 11 Bits 105 MSPS 66 d BFS (typ) 82 d BFS (typ) 1 GHz (typ) 1 W (typ) Applications - - - - - High IF Sampling Receivers Wireless Base Station Receivers Test and Measurement Equipment munications Instrumentation Portable Instrumentation Connection Diagram © 2009 National Semiconductor Corporation .national. .Data Sheet.in Block Diagram Ordering Information Industri...