ADC12662 Datasheet | National Semiconductor

Description Using an innovative multistep conversion technique, the 12-bit ADC12662 CMOS analog-to-digital converter digitizes signals at a 1.5 MHz sampling rate while consuming a maximum of only 200 m W on a single +5V supply. The ADC12662 performs a 12-bit conversion in three lower-resolution “flash” conversions, yielding a fast A/D without the cost and power dissipation associated with true flash approaches. The analog input voltage to the ADC12662 is tracked and held by an internal sampling circuit, allowing high frequency input signals to be accurately digitized without the need for an external sample-and-hold circuit. The ADC12662 features two sample-and-hold/flash parator sections which allow the converter to acquire one sample while converting the previous. This pipelining technique increases conversion speed without sacrificing performance. The multiplexer output is available to the user in order to perform additional external signal processing before the signal is digitized. When the converter is not digitizing signals, it can be placed in the Standby mode; typical power consumption in this mode is 250 µW. Features n n n n Built-in sample-and-hold Single +5V supply Single channel or 2 channel multiplexer operation Low Power Standby mode Key Specifications n n n n n Sampling rate Conversion time Signal-to-Noise Ratio, f IN = 100 k Hz Power consumption (fs = 1.5 MHz) No missing codes over temperature 1.5 MHz (min) 580 ns (typ) 67.5 d B (min) 200 m W (max) Guaranteed Applications n n n n n Digital signal processor front ends Instrumentation Disk drives Mobile telemunications Waveform digitizers ADC12662 Block Diagram Ordering Information Industrial (- 40˚C ≤ TA ≤ +85˚) ADC12662CIV ADC12662CIVF Package V44 Plastic Leaded Chip Carrier VGZ44A Plastic Quad Flat Package © 2001 National Semiconductor Corporation DS011876 .national. Connection Diagrams Top View Top View Pin Descriptions AVCC These are the two positive...