ADC12C170 Datasheet | National Semiconductor

Description Features The ADC12C170 is a high-performance CMOS analog-to- 1.1 GHz Full Power Bandwidth digital converter capable of converting analog input signals - Internal sample-and-hold circuit into 12-Bit digital words at rates up to 170 Mega Samples Per - Low power consumption Second (MSPS). This converter uses a differential, pipelined - Internal precision 1.0V reference architecture with digital error correction and an on-chip sam- Single-ended or Differential clock modes ple-and-hold circuit to minimize power consumption and the external ponent count, while providing excellent dynamic - Clock Duty Cycle Stabilizer performance. A unique sample-and-hold stage yields a full- Dual +3.3V and +1.8V supply operation (+/- 10%) power bandwidth of 1.1 GHz. The ADC12C170 operates from - Power-down and Sleep modes dual +3.3V and +1.8V power supplies and consumes 715 m W - Offset binary or 2's plement output data format of power at 170 MSPS. - Pin-patible with: ADC14155 The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power- 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch) down feature reduces the power consumption to 5 m W while still allowing fast wake-up time to full operation. In addition Key Specifications there is a sleep feature which consumes 50 m W of power and 12 Bits - Resolution has a faster wake-up time. 170 MSPS - Conversion Rate The differential inputs provide a full scale differential input 67.2 d BFS (typ) - SNR (f IN = 70 MHz) swing equal to 2 times the reference voltage. A stable 1.0V 85.4 d BFS (typ) - SFDR (f IN = 70 MHz) internal voltage reference is provided, or the ADC12C170 can ENOB (f IN = 70 MHz) 10.8 bits (typ) - be operated with an external reference. .. 1.1 GHz (typ) - Full Power Bandwidth Clock mode (differential versus single-ended) and output data Power Consumption 715 m W (typ) - format (offset binary versus 2's plement) are pin-selectable. A duty cycle stabilizer maintains...