ADC12L066 Datasheet | National Semiconductor

Description The ADC12L066 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 12-bit digital words at 66 Megasamples per second (MSPS), minimum, with typical operation possible up to 80 MSPS. This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 450 MHz. Operating on a single 3.3V power supply, this device consumes just 357 m W at 66 MSPS, including the reference current. The Power Down feature reduces power consumption to just 50 m W. The differential inputs provide a full scale input swing equal to ± VREF with the possibility of a single-ended input. Full use of the differential input is remended for optimum performance. For ease of use, the buffered, high impedance, single-ended reference input is converted on-chip to a differential reference for use by the processing circuitry. Output data format is 12-bit offset binary. This device is available in the 32-lead LQFP package and will operate over the industrial temperature range of - 40˚C to +85˚C. An evaluation board is available to facilitate the evaluation process. Features n n n n Single supply operation Low power consumption Power down mode On-chip reference buffer Key Specifications n n n n n n n n n Resolution Conversion Rate Full Power Bandwidth DNL SNR (f IN = 10 MHz) SFDR (f IN = 10 MHz) Data Latency Supply Voltage Power Consumption, 66 MHz 12 Bits 66 MSPS 450 MHz ± 0.4 LSB (typ) 66 d B (typ) 80 d B (typ) 6 Clock Cycles +3.3V ± 300 m V 357 m W (typ) Applications n n n n n n n n Ultrasound and Imaging Instrumentation Cellular Base Stations/munications Receivers Sonar/Radar x DSL Wireless Local Loops Data Acquisition Systems DSP Front Ends Connection Diagram TRI-STATE ® is a registered trademark of National Semiconductor...