ADC14155 Datasheet | National Semiconductor

Description The ADC14155 is a high-performance CMOS analog-to-digital converter capable of converting analog input signals into 14-bit digital words at rates up to 155 Mega Samples Per Second (MSPS). This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external ponent count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a fullpower bandwidth of 1.1 GHz. The ADC14155 operates from dual +3.3V and +1.8V power supplies and consumes 967 m W of power at 155 MSPS. The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A powerdown feature reduces the power consumption to 5 m W with the clock input disabled, while still allowing fast wake-up time to full operation. The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14155 can be operated with an external reference. The ADC14155 can be configured for either single-ended or differential operation. Clock mode (differential versus single.. ended) and output data format (offset binary versus 2's plement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14155 is available in a 48-lead LLP package and operates over the industrial temperature range of - 40°C to +85°C. Features - - - - - - - - - - - 1.1 GHz Full Power Bandwidth Internal sample-and-hold circuit Low power consumption Internal precision 1.0V reference Single-ended or Differential clock modes Data Ready output clock Clock Duty Cycle Stabilizer Dual +3.3V and +1.8V supply operation (+/- 10%) Power-down mode Offset binary or 2's plement output data format 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch) Key Specifications - - - - - - - Resolution Conversion Rate SNR (f IN = 70 MHz) SFDR (f...