CD4007M Datasheet | National Semiconductor

Description The CD4007M CD4007C consists of three plementary pairs of N- and P-channel enhancement mode MOS transistors suitable for series shunt applications All inputs are protected from static discharge by diode clamps to VDD and VSS For proper operation the voltages at all pins must be constrained to be between VSS b 0 3V and VDD a 0 3V at all times Features Wide supply voltage range High noise immunity 3 0V to 15V 0 45 VCC (typ ) Connection Diagram Dual-In-Line Package TL F 5943 - 1 Top View Note All P-channel substrates are connected to VDD and all N-channel substrates are connected to VSS Order Number CD4007 C1995 National Semiconductor Corporation TL F 5943 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range CD4007M CD4007C VSS b0 3V to VDD a 0 3V b 55 C to a 125 C b 40 C to a 85 C Storage Temperature Range Power Dissipation (PD) Dual-In-Line Small Outline Operating VDD Range Lead Temperature (Soldering 10 seconds) b 65 C to a 150 C 700 m W 500 m W VSS a 3 0V to VSS a 15V 260 C DC Electrical Characteristics CD4007M Limits Symbol Parameter Conditions Min IL PD VOL VOH VNL VNH IDN IDP II Quiescent Device Current VDD e 5 0V VDD e 10V b 55 C a 25 C a 125 C Units Typ Max Min 0 05 01 0 25 10 0 05 0 05 Typ Max 0 001 0 05 0 001 0 1 0 005 0 25 0 001 1 0 0 0 0 05 0 05 Min Typ Max 30 60 15 60 0 05 0 05 m A m A m W m W V V V V 14 29 V V V V m A m A m A m A p A Quiescent Device VDD e 5 0V Dissipation Package VDD e 10V Output Voltage Low Level Output Voltage High Level Noise Immunity (All Inputs) Noise Immunity (All Inputs) VDD e 5 0V VDD e 10V VDD e 5 0V VDD e 10V VDD e 5 0V VO e 3 6V VDD e 10V VO e 7 2V VDD e 50V VO e 0 95V VDD e 10V VO e 2 9V 36 71 0 75 16 4 95 9 95 4 95 9 95 15 30 35 70 06 13 50 10 2 25 45 2 25 45 10 25 15 30 4 95 9...