CD4012M Datasheet | National Semiconductor

Description These NOR and NAND gates are monolithic plementary MOS (CMOS) integrated circuits The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage This results in high noise immunity over a wide supply voltage range No DC power other than that caused by leakage current is consumed during static conditions All inputs are protected against static discharge and latching conditions Features Wide supply voltage range Low power High noise immunity 3 0V to 15V 10 n W (typ ) 0 45 VDD (typ ) Applications Automotive Data terminals Instrumentation Medical Electronics Alarm system Industrial controls Remote metering puters Connection Diagrams CD4002 Dual-In-Line Package CD4012 Dual-In-Line Package TL F 5940 - 1 TL F 5940 - 2 Top View Order Number CD4002 or CD4012 Top View C1995 National Semiconductor Corporation TL F 5940 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Voltage at Any Pin Operating Temperature Range CD4002M CD4012M CD4002C CD4012C VSS b0 3V to VDD a 0 3V b 55 C to a 125 C b 40 C to a 85 C Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Operating Range (VDD) Lead Temperature (TL) (Soldering 10 seconds) CD4012M Limits b 55 C a 25 C b 65 C to a 150 C 700 m W 500 m W VSS a 3 0V to VSS a 15V 260 C DC Electrical Characteristics CD4002M Symbol IDD PD VOL VOH VNL VNH IDN Parameter Quiescent Device Current Conditions VDD e 5 0V VDD e 10V a 125 C Units m A m A m W m W V V V V V V V V m A m A m A m A m A m A m A m A p A Min Max 0 05 01 0 25 10 0 05 0 05 Min Typ Max Min Max 30 6 15 60 0 05 0 05 0 001 0 05 0 001 0 1 0 005 0 25 0 01 10 0 0 4 95 9 95 15 30 15 30 0 40 09 b0 5 b0 5 Quiescent Device VDD e 5 0V Dissipation Package VDD e 10V Output Voltage...