CD4042BM Datasheet | National Semiconductor

Description The CD4042BM CD4042BC quad clocked ‘‘D’’ latch is a monolithic plementary MOS (CMOS) integrated circuit constructed with P- and N-channel enhancement mode transistors The outputs Q and Q either latch or follow the data input depending on the clock level which is programmed by the polarity input For polarity e 0 the information present at the data input is transferred to Q and Q during 0 clock level and for polarity e 1 the transfer occurs during the 1 clock level When a clock transition occurs (positive for polarity e 0 and negative for polarity e 1) the information present at the input during the clock transition is retained at the outputs until an opposite clock transition occurs Features Wide supply voltage range High noise immunity Low power TTL patibility Clock polarity control Fully buffered data inputs Q and Q outputs 3 0V to 15V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS Connection Diagram Dual-In-Line Package Truth Table Clock 0 L 1 K Polarity 0 0 1 1 Q D Latch D Latch Order Number CD4042B TL F 5966 - 1 Top View Logic Diagrams TL F 5966 - 2 TL F 5966 - 3 TL F 5966 - 4 C1995 National Semiconductor Corporation TL F 5966 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds) b 0 5V to a 18V b 0 5V to VDD a 0 5V b 65 C to a 150 C Remended Operating Conditions (Note 2) Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4042BM CD4042BC 3V to 15V 0V to VDD b 55 C to a 125 C b 40 C to a 85 C 700 m W 500 m W 260 C DC Electrical Characteristics CD4042BM (Note 2) Symbol IDD Parameter Conditions b 55 C a 25 C a 125 C Units m A m A m A V V V V V V Min...