CD4044BC Datasheet | National Semiconductor

Description CD4043BM CD4043BC are quad cross-couple TRI-STATE CMOS NOR latches and CD4044BM CD4044BC are quad cross-couple TRI-STATE CMOS NAND latches Each latch has a separate Q output and individual SET and RESET inputs There is a mon TRI-STATE ENABLE input for all four latches A logic ‘‘1’’ on the ENABLE input connects the latch states to the Q outputs A logic ‘‘0’’ on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output The TRI-STATE feature allows mon bussing of the outputs Features Y Y Y Y Y Y Wide supply voltage range 3V to 15V Low power 100 n W (typ ) High noise immunity 0 45 VDD (typ ) Separate SET and RESET inputs for each latch NOR and NAND configuration TRI-STATE output with mon output enable Applications Multiple bus storage Strobed register Four bits of independent storage with output enable General digital logic Connection Diagrams CD4043BM CD4043BC Dual-In-Line and Flat Packages CD4044BM CD4044BC Dual-In-Line and Flat Packages TL F 5967 - 3 TL F 5967 - 4 Top View Top View Order Number CD4043B or CD4044B Truth Table CD4043BM CD4043BC S X 0 1 0 1 R X 0 0 1 1 E 0 1 1 1 1 Q OC NC 1 0 D CD4044BM CD4044BC S X 1 0 1 0 R X 1 1 0 0 E 0 1 1 1 1 Q OC NC 1 0 DD OC NC X D DD TRI-STATE No change Don’t care Dominated by S e 1 input Dominated by R e 0 input C1995 National Semiconductor Corporation TL F 5967 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VDD) Input Voltage (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering 10 seconds) b 0 5V to a 18V b 0 5V to VDD a 0 5V b 65 C to a 150 C Remended Operating Conditions (Note 2) Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) CD4043BM...