COP8SAB5 Datasheet | National Semiconductor

Description Note: COP8SAx devices are instruction set and pin patible supersets of the COP800 Family devices, and are replacements for these in new designs when possible. The COPSAx Rom based and OTP microcontrollers are highly integrated COP8™ feature core devices, with 1k to 4k memory and advanced features including low EMI. These single-chip CMOS devices are suited for low cost applications requiring a full featured controller, low EMI, and POR. 100% form-fit-function patible OTP versions are available with 1k, 2k, and 4k memory, and in a variety of packages including 28-pin CSP. Erasable windowed versions are available for use with a range of COP8 software and hardware development tools. Memory (bytes) 1k ROM 2k ROM 4k ROM 1k OTP EPROM 2k OTP EPROM 4k OTP EPROM 1k OTP EPROM 2k OTP EPROM 4k OTP EPROM 4k EPROM 4k EPROM RAM (bytes) 64 128 128 64 128 128 64 128 128 128 128 I/O Pins 12/16/24 16/24 16/24/36/40 12/16/24 16/24 16/24 24 24 24 16/24/36 40 Family features include an 8-bit memory mapped architecture, 10 MHz CKI with 1 µs instruction cycle, one multifunction 16-bit timer/counter with PWM output, MICROWIRE/PLUS™ serial I/O, two power saving HALT/ IDLE modes, MIWU, idle timer, on-chip R/C oscillator, 12 high current outputs, user selectable options (WATCHDOG™, 4 clock/oscillator modes, power-on-reset), low EMI 2.7V to 5.5V operation, and 16/20/28/40/44 pin packages. Devices included in this datasheet are: Device COP8SAA5 COP8SAB5 COP8SAC5 COP8SAA7 COP8SAB7 COP8SAC7 COP8SAA7SLB9 COP8SAB7SLB9 COP8SAC7SLB9 COP8SAC7-Q3 COP8SAC7-J3 Packages 16/20/28 DIP/SOIC 20/28 DIP/SOIC 20/28 DIP/SOIC, 28 CSP, 40 DIP, 44 PLCC/QFP 16/20/28 DIP/SOIC 20/28 DIP/SOIC 20/28 DIP/SOIC, 28 CSP, 40 DIP, 44 PLCC/QFP 28 CSP 28 CSP 28 CSP 20/28/40 DIP 44 PLCC Temperature 0 to +70˚C, -40 to +85˚C, -40 to +125˚C 0 to +70˚C, -40 to +85˚C, -40 to +125˚C 0 to +70˚C, -40 to +85˚C, -40 to +125˚C 0 to +70˚C, -40 to +85˚C, -40 to +125˚C 0 to +70˚C, -40 to +85˚C, -40 to +125˚C 0 to +70˚C, -40 to...