CS4103 Datasheet | National Semiconductor

Description The National Semiconductor® Geode™ CS4103 is a three crystal or a 24.576 MHz clock input. The CS4103 operates port 400 Mbit/sec IEEE 1394 Physical Layer (PHY) device. from a single 3.3V supply and supports transfers at 98.304, The CS4103 plies to revision 2.0 of the P1394a specifi- 196.608, and 393.216 Mbit/sec, (usually referred to as 100, cation. The device is a three port implementation of a reusable cell design scalable from one to sixteen ports. The CS4103 supports all of the P1394a enhancements including connection debounce, arbitrated reset, ack-accelerated arbitration, fly-by concatenation, multi-speed packet concatenation, PHY pinging, priority arbitration, and Suspend/Resume operation. It also implements the standard te PHY-Link interface defined in IEEE specification 1394-1995 and updated in the P1394a specification for direct connection with the Geode CS4210 IEEE 1394 Open Host Controller Interface (OHCI) device. The interface can operate in either direct or isolated mode and supports single capacitor isolation with bus hold inputs. le The CS4103 provides a plete PHY solution including all bias generation, differential line drivers and receivers, single ended parators for speed signaling, speed signaling current sources, bias detect, and connect detect circuitry per port. It includes data and strobe encoding/ decoding functions as well as a re-time FIFO to synchro- o nize the receive data to the local clock domain. The CS4103 can receive and respond to all the PHY packet types defined in revision 2.0 of the P1394a specification. It also supports Suspend and Resume port states and con- s nect detect functions. The CS4103 generates the internal clocks and the Link SCLK (System Clock) based on a 24.576 MHz external 200, and 400 Mbit/sec respectively). Features IEEE 1394 Physical Layer Device (PHY) pliant with revision 2.0 of P1394a including all enhancements Scalable design from one to sixteen ports Supports data rates of 100, 200,...