DM54122 Datasheet | National Semiconductor

Description The ’122 features positive and negative DC level triggering inputs plementary outputs an optional 10 k X internal timing resistor and an overriding Direct Clear (CD) input When the circuit is in the quasi-stable (delay) state another trigger applied to the inputs (per Truth Table) will cause the delay period to start again without disturbing the outputs This process can be repeated indefinitely and thus the output pulse period (Q HIGH Q LOW) can be made as long as desired Alternatively a delay period can be terminated by a LOW signal applied to CD which also prevents triggering An internal connection from CD to the input gate makes it possible to trigger the circuit by a positive-going signal on CD as shown in the Truth Table For timing capacitor values greater than 1000 p F the output pulse width is defined as follows tw e 0 32 RXCX (1 0 a 0 7 RX) Where tw is in ns RX is in k X and CX is in p F Connection Diagram Dual-In-Line Package Logic Symbol TL F 10212 - 2 TL F 10212 - 1 Order Number 54122DMQB 54122FMQB or DM74122N See NS Package Number J14A N14A or W14B VCC e Pin 14 GND e Pin 7 NC e Pins 10 and 12 Pin Names A1 A2 B1 B2 CD Q Q Description Trigger Inputs (Active Falling Edge) Trigger Inputs (Active Rising Edge) Direct Clear Inputs (Active LOW) Outputs C1995 National Semiconductor Corporation TL F 10212 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings The ‘‘Remended Operating Conditions’’ table will define the conditions for actual device operation If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 5 5V...