DM74LS952 Datasheet | National Semiconductor

Description These circuits are TRI-STATE edge-triggered 8-bit I O registers in parallel with 8-bit serial shift registers which are capable of operating in any of the following modes parallel load from I O pins to register ‘‘A’’ parallel transfer down from register ‘‘A’’ to serial shift register ‘‘B’’ parallel transfer up from shift register ‘‘B’’ to register ‘‘A’’ serial shift of register ‘‘B’’ synchronously clear Since the registers are edgetriggered by the positive transition of the clock the control lines which determine the mode or operation are pletely independent of the logic level applied to the clock Designed for bus-oriented systems these circuits have their TRI-STATE inputs and outputs on the same pins Features Y Y Y Y Y Registers are edge-triggered by the positive transition of the clock All inputs are PNP transistors Input disable dominates over output disable Output high impedance state does not impede any other mode of operation 8-bit I O pins are TRI-STATE buffers Typical shift frequency is 36 MHz Typical power dissipation is 305 m W All control inputs are active when in an ‘‘L’’ logic state Devices can be cascaded into N-bit word Connection Diagram Dual-In-Line Package Pin Description DISO Output disable IS Serial input DISI Input disable DISTU Transfer up disable DISTD Transfer down disable DISS Shift disable OS Serial output CLK Clock GND Ground I O1 I O 8 8-bit I O pins VCC Supply Voltage TL F 6437 - 1 Top View Order Number DM74LS952N or DM86LS52N See NS Package Number N18A TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 6437 RRD-B30M105 Printed in U S A Data Sheet 4 U . .. Absolute Maximum Ratings (Note) Supply Voltage Input Voltage Operating Free Air Temperature Range DM74LS DM86LS 7V 7V Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The...