DM74S195 Datasheet | National Semiconductor

Description These 4-bit registers feature parallel inputs parallel outputs J-K serial inputs shift load control input and a direct overriding clear All inputs are buffered to lower the input drive requirements The registers have two modes of operation Parallel (broadside) load Shift (in the direction QA toward QD) Parallel loading is acplished by applying the four bits of data and taking the shift load control input low The data is loaded into the associated flip-flop and appears at the outputs after the positive transition of the clock input During loading serial data flow is inhibited Shifting is acplished synchronously when the shift load control input is high Serial data for this mode is entered at the J-K inputs These inputs permit the first stage to perform as a J-K D or T-type flip-flop as shown in the truth table The high-performance S195 with a 105 MHz typical shift frequency is particularly attractive for very high-speed data processing systems In most cases existing systems can be upgraded merely by using this Schottky-clamped shift register Features Y Synchronous parallel load Y Positive-edge-triggered clocking Y Parallel inputs and outputs from each flip-flop Y Direct overriding clear Y J and K inputs to first stage Y plementary outputs from last stage Y For use in high-performance accumulators processors serial-to-parallel parallel-to-serial converters Y Typical clock frequency 105 MHz Y Typical power dissipation 350 m W Connection Diagram Dual-In-Line Package Order Number DM54S195J or DM74S195N See NS Package Number J16A or N16E TL F 6476 - 1 C1995 National Semiconductor Corporation TL F 6476 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 5 5V Operating Free Air Temperature Range DM54S b55 C to a125 C DM74S 0 C to a70 C Storage...