DP83231 Datasheet | National Semiconductor

Description The DP83231 CRD device is a clock recovery device that has been designed for use in 100 Mbps FDDI (Fiber Distributed Data Interface) networks The device receives serial data from a Fiber Optic Receiver in differential ECL NRZI 4B 5B group code format and outputs resynchronized NRZI received data and a 125 MHz received clock in differential ECL format for use by the DP83251 55 PLAYERTM device Features Clock recovery at 100 Mbps data rate Internal 250 MHz VCO 0 1% VCO operating range Crystal controlled Precision window centering delay line Single a 5V supply 28-pin PLCC package Bi CMOS processing TL F 10384 - 1 FIGURE 1-1 FDDI Chip Set Block Diagram TRI-STATE is a registered trademark of National Semiconductor Corporation BSITM BMACTM PLAYERTM CDDTM and CRDTM are trademarks of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 10384 RRD-B30M105 Printed in U S A Table of Contents 1 0 FDDI CHIP SET OVERVIEW 2 0 FUNCTIONAL DESCRIPTION 3 0 PIN DESCRIPTIONS 4 0 ELECTRICAL CHARACTERISTICS 4 1 Absolute Maximum Ratings 4 2 Remended Operating Conditions 4 3 DC Electrical Characteristics 4 3 AC Electrical Characteristics 5 0 DETAILED INFORMATION 5 1 Special External ponents 5 2 Layout Remendations 5 3 Input and Output Schematics 5 4 Debug Procedure 5 5 AC Test Circuits 1 0 FDDI Chip Set Overview National Semiconductor’s FDDI chip set consists of five ponents as shown in Figure 1-1 For more information about the other devices in the chip set consult the appropriate data sheets and application notes DP83261 BMAC TM Device Media Access Controller The BMAC device implements the Timed Token Media Access Control protocol defined by the ANSI FDDI X3T9 5 MAC Standard DP83231 CRD TM Device Clock Recovery Device The Clock Recovery Device extracts a 125 MHz clock from the ining bit stream Features All of the standard defined ring service options Full duplex operation with through parity Supports all FDDI Ring...