DP83847 Datasheet | National Semiconductor

Description Features The DP83847 is a full feature single Physical Layer device s Low-power 3.3V, 0.18µm CMOS technology with integrated PMD sublayers to support both 10BASE-T s Power consumption < 351m W (typical) and 100BASE-TX Ethernet protocols over Category 3 (10 s 5V tolerant I/Os Mb/s) or Category 5 unshielded twisted pair cables. s 5V/3.3V MAC interface The DP83847 is designed for easy implementation of 10/100 Mb/s Ethernet home or office solutions. It interfaces s IEEE 802.3 ENDEC, 10BASE-T transceivers and filters to Twisted Pair media via an external transformer. This s IEEE 802.3u PCS, 100BASE-TX transceivers and filters device interfaces directly to MAC devices through the IEEE s IEEE 802.3 pliant Auto-Negotiation 802.3u standard Media Independent Interface (MII) ensuring interoperability between products from different ven- s Output edge rate control eliminates external filtering for Transmit outputs dors. s Base Line Wander pensation The DP83847 utilizes on chip Digital Signal Processing (DSP) technology and digital Phase Lock Loops (PLLs) for s IEEE 802.3u MII (16 pins/port) robust performance under all operating conditions, s LED support (Link, Rx, Tx, Duplex, Speed, Collision) enhanced noise immunity, and lower external ponent s Single register access for plete PHY status count when pared to analog solutions. s 10/100 Mb/s packet loopback BIST (Built in Self Test) s 56-pin LLP package (9w) x (9l) x (.75h) mm Applications s LAN on Motherboard s Embedded Applications System Diagram Magnetics Ethernet MAC MII 10/100 Mb/s Ds PHYTER II RJ-45 10BASE-T or 100BASE-TX 25 MHz Clock Status LEDs Typical Ds PHYTER II application ©2002 National Semiconductor Corporation .national. MII HARDWARE CONFIGURATION PINS (AN_EN, AN0, AN1) (PAUSE_EN) (LED_CFG, PHYAD) SERIAL MANAGEMENT MDIO MDC RX_ER RX_DV TX_ER TX_EN COL CRS RXD[3:0] TXD[3:0] MII INTERFACE/CONTROL RX_DATA RX_CLK TX_DATA TX_DATA TX_CLK REGISTERS MII PHY ADDRESS NRZ TO...