DP83848C Datasheet | National Semiconductor

Description Features The DP83848C is a robust fully featured 10/100 single - Low-power 3.3V, 0.18µm CMOS technology port Physical Layer device offering low power consumption, including several intelligent power down states. These low power modes increase overall product reliability due to decreased power dissipation. Sup- - Low power consumption < 270m W Typical - 3.3V MAC Interface - Auto-MDIX for 10/100 Mb/s porting multiple intelligent power modes allows the application to use the absolute minimum amount of power needed for operation. The DP83848C includes a 25MHz clock out. This means that the application can be designed with a - Energy Detection Mode - 25 MHz clock out - SNI Interface (configurable) - RMII Rev. 1.2 Interface (configurable) minimum of external parts, which in turn results in the - MII Serial Management Interface (MDC and MDIO) lowest possible total cost of the solution. - IEEE 802.3u MII The DP83848C easily interfaces to twisted pair media via an external transformer. Both MII and RMII are supported ensuring ease and flexibility of design. The DP83848C features integrated sublayers to support both 10BASE-T and 100BASE-TX Ethernet protocols, which ensures patibility and interoperability with all other standards based Ethernet solutions. - IEEE 802.3u Auto-Negotiation and Parallel Detection - IEEE 802.3u ENDEC, 10BASE-T transceivers and filters - IEEE 802.3u PCS, 100BASE-TX transceivers and filters - Integrated ANSI X3.263 pliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander pensation The DP83848C is offered in a small form factor (48 pin - Error-free Operation up to 137 meters LQFP) so that a minimum of board space is needed. - Programmable LED support Link, 10 /100 Mb/s Mode, Activ- ity, and Collision Detect Applications - Single register access for plete PHY status - High End Peripheral Devices - Industrial Controls and Factory Automation - 10/100 Mb/s packet BIST (Built in Self Test) - 48-pin LQFP...