DS25BR100 Datasheet | National Semiconductor

Description The DS25BR100 is a single channel 3.125 Gbps LVDS buffer optimized for high-speed signal transmission over lossy FR-4 printed circuit board backplanes and balanced metallic cables. Fully differential signal paths ensure exceptional signal integrity and noise immunity. The DS25BR100 features transmit pre-emphasis (PE) and receive equalization (EQ), making it ideal for use as a repeater device. Other LVDS devices with similar IO characteristics include the following products. The DS25BR120 features four levels of pre-emphasis for use as an optimized driver device, while the DS25BR110 features four levels of equalization for use as an optimized receiver device. The DS25BR150 is a buffer/repeater with the lowest power consumption and does not feature transmit pre-emphasis nor receive equalization. Wide input mon mode range allows the receiver to accept signals with LVDS, CML and LVPECL levels; the output levels are LVDS. A very small package footprint requires minimal space on the board while the flow-through pinout allows easy board layout. The differential inputs and outputs are internally terminated with a 100Ω resistor to lower device input and output return losses, reduce ponent count, and further minimize board space. Features - DC - 3.125 Gbps low jitter, high noise immunity, low power operation - Receive equalization reduces ISI jitter due to media loss - Transmit pre-emphasis drives lossy backplanes and cables - On-chip 100Ω input and output termination minimizes insertion and return losses, reduces ponent count and minimizes board space - 7 k V ESD on LVDS I/O pins protects adjoining ponents - Small 3 mm x 3 mm 8-LLP space saving package Applications - Clock and data buffering - Metallic cable driving and equalization - FR-4 equalization Typical Application © 2007 National Semiconductor Corporation .national. Block Diagram Pin Diagram Pin Descriptions Pin Name EQ IN+ INPE NC OUTOUT+ VCC...