DS25C400 Datasheet | National Semiconductor

Description The DS25C400 is a four-channel serializer/deserializer (SERDES) for high-speed serial data transmission over controlled impedance transmission media such as a printed circuit board backplane or twin-axial cable. It is capable of transmitting and receiving serial data of 2.125 - 2.5 Gbps or 1.0625 - 1.25 Gbps per channel. Each transmit section of the DS25C400 contains a low-jitter clock synthesizer, an 8-bit or 10-bit parallel to serial converter with built in 8b/10b encoder, and a CML output driver with selectable pre-emphasis optimized for backplane applications. Its receive section contains an input limiting amplifier with on-chip terminations and selectable equalization levels, a clock/data recovery PLL, a ma detector and a serial to parallel converter with built-in 8b/10b decoder. The DS25C400 has built-in local loopback test mode, pseudo-random pattern generator and error detector to support self-testing. The DS25C400 requires no external ponents for its clock synthesizers and clock recovery PLL’s. Three external resistors are needed to set the proper bias currents and pensate for process variations to achieve tight tolerance on-chip terminations. Features n Quad Serializer/Deserializer n Data rate per channel: 2.125 - 2.5 Gbps or 1.0625 1.25 Gbps n Supports 106.25 - 125 MHz differential reference input clock n Low jitter clock synthesizers for clock distribution n 8-bit or 10-bit parallel I/O Interface conforms to SSTL_18 Class 1 (also interfaces to 1.8V HSTL or 1.8V LVCMOS) n On-chip 8b/10b encoder and decoder n High speed serial CML drivers n High speed serial CML on-chip terminations n Selectable pre-emphasis and equalization n On-chip ma Detect for character alignment n On-chip local loopback test mode n On-chip pattern generator and error checker to support BIST n Hot plug protection n Low power, 420 m W (typ) per channel n 324-ball TE-PBGA package n Operating temperature - 40˚C to +85˚C General Function Diagram © 2002 National...