DS38EP100 Datasheet | National Semiconductor

Description National’s Power-saver equalizer pensates for transmission medium losses and minimizes medium-induced deterministic jitter. Performance is guaranteed over the full range of 1 to 5 Gbps. The DS38EP100 requires no power to operate. The equalizer operates anywhere in the data path to minimize media-induced deterministic jitter in both FR4 and cable applications. Symmetric I/O structures support full duplex or half duplex applications. Linear pensation is provided independent of line coding or protocol. The device is ideal for both bi-level and multi-level signaling. The equalizer is available in a 6 pin leadless LLP package with a space saving 2.2 mm X 2.5 mm footprint. This tiny package provides maximum flexibility in placement and routing of the Power-saver equalizer. Features - - - - - - - - - - - - - 1 to 5 Gbps Operation No Power or Ground Required Equalization effective anywhere in data path Equalizes CML, LV-PECL, LVDS signals Symmetric I/O structures provide equal boost for bidirectional operation 7 d B Maximum Boost Code independent, 8b/10b or Scrambled Supports both bi-level and multi-level signaling Extends reach over backplanes and cables patible with PCI-Express Gen1 and Gen2 patible with XAUI Operates in series with existing active Equalizer Easy to handle 6 pin LLP Simplified Application Diagram Note: The DS38EP100 provides the flexibility of passing the data from either side of the device. It can be placed anywhere in the data path.. © 2007 National Semiconductor Corporation .national. .. Pin Descriptions Pin Name High Speed Differential I/O IOAIOA+ IOBIOB+ NC Exposed Pad Note: I = Input / O = Output Pin Number 3 1 4 6 2, 5 DAP I/O, Type I/O I/O N/A Description Symmetric differential I/O. Symmetric differential I/O. Reserved. Do not connect. Pin Diagram Bottom View shown 2.2mm x 2.5mm 6-Pin LLP Package Order number DS38EP100 .national. .. Absolute Maximum Ratings (Note 1) If...