DS40MB200 Datasheet | National Semiconductor

Description The DS40MB200 is a dual signal conditioning 2:1 multiplexer and 1:2 fan-out buffer designed for use in backplane redundancy applications. Signal conditioning features include input equalization and programmable output preemphasis that enable data munication in FR4 backplanes up to 4 Gb/s. Each input stage has a fixed equalizer to reduce ISI distortion from board traces. All output drivers have 4 selectable steps of pre-emphasis to pensate for transmission losses from long FR4 backplanes and reduce deterministic jitter. The pre-emphasis levels can be independently controlled for the line-side and switch-side drivers. The internal loopback paths from switch-side input to switchside output enable at-speed system testing. All receiver inputs and driver outputs are internally terminated with 100Ω differential terminating resistors Features Dual 2:1 multiplexer and 1:2 buffer 1- 4 Gbps fully differential data paths Fixed input equalization Programmable output pre-emphasis Independent switch and line side pre-emphasis controls Programmable switch-side loopback mode On-chip terminations +3.3V supply Low power, 1W max ESD rating HBM 6 k V Lead-less LLP-48 package (7mmx7mmx0.8mm, 0.5mm pitch) n 0˚C to +85˚C operating temperature range n n n n n n n n n n n Functional Block Diagram .. © 2005 National Semiconductor Corporation DS200217 .national. .. Simplified Block Diagram .national. Connection Diagram .. Order number DS40MB200SQ See NS Package Number SQA48D .national. Pin Descriptions Pin Name Pin Number 6 7 33 34 30 31 9 10 46 45 4 3 40 39 43 42 22 21 28 27 16 15 19 18 37 13 12 1 36 25 47 48 23 24 26 I I/O Description LINE SIDE HIGH SPEED DIFFERENTIAL IO’s LI_0+ LI_0- LO_0+ LO_0- LI_1+ LI_1- LO_1+ LO_1- SOA_0+ SOA_0- SOB_0+ SOB_0- SIA_0+ SIA_0- SIB_0+ SIB_0- SOA_1+ SOA_1- SOB_1+ SOB_1- SIA_1+ SIA_1- .. Inverting and non-inverting differential inputs of port_0 at the line...