DS90UR906Q Datasheet | National Semiconductor

Description The DS90UR905Q/906Q chipset translates a parallel RGB Video Interface into a high-speed serialized interface over a single pair. This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. The DS90UR905Q Ser (serializer) embeds the clock, balances the data payload, and level shifts the signals to highspeed low voltage differential signaling. Up to 24 inputs are serialized along with the three video control signals. This supports full 24-bit color or 18-bit color and 6 general purpose signals (e.g. Audio I2S) applications. The DS90UR906Q Des (deserializer) recovers the data (RGB) and control signals and extracts the clock from the serial stream. It is able to lock to the ining data stream without the use of a training sequence or special SYNC patterns, and does not require a reference clock. A link status (LOCK) output signal is provided. Serial transmission is optimized by a user selectable de-emphasis, differential output level select features , and receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking patibility. The Des may be configured to generate Spread Spectrum Clock and Data on its parallel outputs. The DS90UR905Q (Ser) is offered in a 48-pin LLP and the DS90UR906Q (Des) is offered in a 60-pin LLP package. They are specified over the automotive AEC-Q100 grade 2 temperature range of -40°C to +105°C. Features - - - - - - - - - - - 5 - 65 MHz PCLK support (140 Mbps - 1.82 Gbps) AC coupled STP interconnect cable up to 10 meters Integrated terminations on Ser and Des @ Speed link BIST mode and reporting pin Optional I2C patible Serial Control Bus RGB888 + VS, HS, DE support Power down mode minimizes power...