DS92LV0422 Datasheet | National Semiconductor

Description The DS92LV0421 (serializer) and DS92LV0422 (deserializer) chipset translates a Channel Link LVDS video interface (4 LVDS Data + LVDS Clock) into a high-speed serialized interface over a single CML pair. The DS92LV0421 and DS92LV0422 enable applications that currently use the popular Channel Link or Channel Link style devices to seamlessly upgrade to an embedded clock interface to reduce interconnect cost or ease design challenges. The parallel LVDS interface also reduces FPGA I/O pins, board trace count and alleviates EMI issues, when pared to traditional single-ended wide bus interfaces. Programmable transmit de-emphasis, receive equalization, on-chip scrambling and DC balancing enables longer distance transmission over lossy cables and backplanes. The Deserializer automatically locks to ining data without an external reference clock or special sync patterns, providing easy “plug-and-go” operation. The DS92LV0421 and DS92LV0422 are programmable though an I2C interface as well as by pins. A built-in ATSPEED BIST feature validates link integrity and may be used for system diagnostics. The DS92LV0421 and DS92LV0422 can be used interchangeably with the DS92LV2421 or DS92LV2422. This allows designers the flexibility to connect to the host device and receiving devices with different interface types, LVDS or LVCMOS. Features - 5-channel (4 data + 1 clock) Channel Link LVDS parallel - - - - - - - - interface supports 24-bit data 3-bit control at 10 - 75 MHz AC Coupled STP Interconnect up to 10 meters in length Integrated serial CML terminations AT- SPEED BIST Mode and status pin Optional I2C patible Serial Control Bus Power Down Mode minimizes power dissipation 1.8V or 3.3V patible control pin interface >8 k V ESD (HBM) protection -40° to +85°C temperature range SERIALIZER - DS92LV0421 - Data scrambler for reduced EMI - DC- balance encoder for AC coupling - Selectable output VOD and adjustable de-emphasis DESERIALIZER - DS92LV0422 - Random data lock; no...