DS92LV090A Datasheet | National Semiconductor

Description The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides mon mode noise rejection of ± 1V. The receiver threshold is less than ± 100 m V over a ± 1V mon mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Applications Information Section for more details.) Features n n n n n n n n n n n n n n n n Bus LVDS Signaling 3.2 nanosecond propagation delay max Chip to Chip skew ± 800ps Low power CMOS design High Signaling Rate Capability (above 100 Mbps) 0.1V to 2.3V mon Mode Range for VID = 200m V ± 100 m V Receiver Sensitivity Supports open and terminated failsafe on port pins 3.3V operation Glitch free power up/down (Driver & Receiver disabled) Light Bus Loading (5 p F typical) per Bus LVDS load Designed for Double Termination Applications Balanced Output Impedance Product offered in 64 pin TQFP package High impedance Bus pins on power off (VCC = 0V) Driver Channel to Channel skew (same device) 230ps typical n Receiver Channel to Channel skew (same device) 370ps typical Simplified Functional Diagram DS100111-1 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2000 National Semiconductor Corporation DS100111 .national. Connection Diagram DS100111-2 Top View...