DS99R124Q Datasheet | National Semiconductor

Description The DS99R124Q converts FPD-Link II to FPD-Link. It translates a high-speed serialized interface with an embedded clock over a single pair (FPD-Link II) to three LVDS data/control streams and one LVDS clock pair (FPD-Link). This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects. The DS99R124Q converter recovers the data (RGB) and control signals and extracts the clock from a serial stream (FPD-Link II). It is able to lock to the ining data stream without the use of a training sequence or special SYNC patterns and does not require a reference clock. A link status (LOCK) output signal is provided. Adjustable input equalization of the serial input stream provides pensation for transmission medium losses of the cable and reduces the medium-induced deterministic jitter. EMI is minimized by the use of low voltage differential signaling, output state select feature , and additional output spread spectrum generation. With fewer wires to the physical interface of the display, FPDLink output with LVDS technology is ideal for high speed, low power and low EMI data transfer. The DS99R124Q is offered in a 48-pin LLP package and is specified over the automotive AEC-Q100 Grade 2 temperature range of -40˚C to +105˚C. Features - - - - - - - - - - - - - - - - - 5 - 43 MHz support (140 Mbps to 1.2 Gbps Serial Link) 4-channel (3 data + 1 clock) FPD-Link LVDS outputs 3 low-speed over-sampled LVCMOS outputs AC Coupled STP Interconnect up to 10 meters in length Integrated input termination @ Speed link BIST mode and reporting pin Optional I2C patible Serial Control Bus RGB666 + VS, HS, DE converted from 1 pair Power down mode minimizes power dissipation FAST random data lock; no reference clock required Adjustable input receive...