FPD87346 Datasheet | National Semiconductor

Description The FPD87346 is a timing controller that bines an LVDS single pixel input interface with National’s Reduced Swing Differential Signaling (RSDS™) output driver interface for (SVGA) XGA and Wide XGA resolutions. It resides on the TFT-LCD panel and provides the data buffering and control signal generation for (SVGA) XGA, and Wide XGA graphic modes. The RSDS™ path to the column driver contributes toward lowering radiated EMI and reducing system dynamic power consumption. This single RSDS™ bus conveys the 8-bit color data for (SVGA) XGA, and Wide XGA panels at 170 Mb/s when using VESA 60 Hz standard timing. Features n Reduced Swing Differential Signalling (RSDS™) digital bus reduces dynamic power, EMI and bus width from the timing controller n LVDS single pixel input interface system n Input clock range from 40 MHz to 85 MHz n Drives RSDS™ Column Drivers at 170 Mb/s with an 85 MHz clock (Max.) n Virtual 8 bit color depth in FRC/Dithering mode n Single narrow 9-bit differential Source Driver bus minimizes width of Source PCB n Ability to drive (SVGA) XGA and Wide XGA TFT-LCD Systems n Failure detect function in DE mode n CMOS circuitry operates from a 3.0V- 3.6V supply System Diagram FIGURE 1. Block Diagram of the LCD Module RSDS™ is a trademark of National Semiconductor Corporation © 2003 National Semiconductor Corporation DS200615 .national. Block Diagram FIGURE 2. Block Diagram Functional Description FPD-LINK RECEIVER The LVDS based FPD-Link Receiver inputs video data and control timing through 4-LVDS channels plus clock to provide 24-bit color or 3-LVDS channels can be used for 18-bit color. The video data is converted to a parallel data stream and routed to the 8-6 bit translator. SPREAD SPECTRUM SUPPORT The FPD-Link receiver supports graphics controllers with Spread Spectrum interfaces for reducing EMI. The Spread Spectrum methods supported are Center and Down Spread. A maximum of 2% total is supported at a...