INS8154 Datasheet | National Semiconductor

Description The RAM Input/Output Chip if'.' LSI device wh/ch provides random access memor' Peripheral interfacing for microputer syste he RAM portion contains 1024 bits of static R anized as 128x8, The 1/0 portion consists of t ripheral ports of eight bits each. Each of the 1/0 im ln the two ports may be defined as an input or': -output to provide maximum flexibility. Each port iv be read from or written to in a parallel (8-bit b ' (mode. To improve efficiency and simplify programrijing in control-based applications, a single bit of 1/0 II' either port may be Set, cleared or read with a single rrilc TOprocessor instruction. ,ln addition to basic 1/0, oneof the ports, port A, may be programmed to operate!1 in several types of strobed mode with handshake. St(obed mode together with optional interrupt operation permit both high speed parallel data transfers and:, interface to a wide variety of peripherals with no external logic. The RAM 1/0 is an n-channe! silicon gate device packaged in a 40-pin dual-in-li". package. It operates ',y and is fully TTL ~th a single 5.volt power SUIt P c<Jmpatible. ~r RIL 1118 z en CD CIl ~ .... .. ~ ~ Features 0 0 0 0 0 0 ::r m . 128x8RAM Single +5-volt power s' pl V Low power dissipatio .... 0 0 0 0 0 Fully static operation pletely TTL Two 8-bit programma 1/0 port A has TRI-S ~ CD ibl~Î" ji c::r . '1/0 ports ;J'El!!> capability Handshake controls Single bit 1/0 operati Reduces system packs strobed mode of operation with single instruction cou nt '< ëo t U _0 - Direct interface with Independent operatio" " , JMP f RAM and 1/0 MICROBUS"TM- fible , , MICROBUSTM Configuration ~ "g C 0' C 't J C -::a » s: ::a » i: ADDRESS BUS CPU' GRO~ DATA BUS CONTRDl BUS M 1 C PORT BUS '1'...