LM2524D Datasheet | National Semiconductor

Description The LM3524D family is an improved version of the industry standard LM3524. It has improved specifications and additional features yet is pin for pin patible with existing 3524 families. New features reduce the need for additional external circuitry often required in the original version. The LM3524D has a ± 1% precision 5V reference. The current carrying capability of the output drive transistors has been raised to 200 m A while reducing VCEsat and increasing VCE breakdown to 60V. The mon mode voltage range of the error-amp has been raised to 5.5V to eliminate the need for a resistive divider from the 5V reference. In the LM3524D the circuit bias line has been isolated from the shut-down pin. This prevents the oscillator pulse amplitude and frequency from being disturbed by shut-down. Also at high frequencies ( ≅ 300 k Hz) the max. duty cycle per output has been improved to 44% pared to 35% max. duty cycle in other 3524s. In addition, the LM3524D can now be synchronized externally, through pin 3. Also a latch has been added to insure one pulse per period even in noisy environments. The LM3524D includes double pulse suppression logic that insures when a shut-down condition is removed the state of the T-flip-flop will change only after the first clock pulse has arrived. This feature prevents the same output from being pulsed twice in a row, thus reducing the possibility of core saturation in push-pull designs. Features n n n n n n n n n Fully interchangeable with standard LM3524 family ± 1% precision 5V reference with thermal shut-down Output current to 200 m A DC 60V output capability Wide mon mode input range for error-amp One pulse per period (noise suppression) Improved max. duty cycle at high frequencies Double pulse suppression Synchronize through pin 3 Block Diagram DS008650-1 © 1999 National Semiconductor Corporation DS008650 .national. Absolute Maximum Ratings (Note 5) If Military/Aerospace specified devices are required, please contact the...