LM5025A Datasheet | National Semiconductor

Description The LM5025A is a functional variant of the LM5025 active clamp PWM controller. The functional differences of the LM5025A are: The CS1 and CS2 current limit thresholds have been increased to 0.5V. The internal CS2 filter discharge device has been disabled and no longer operates each clock cycle. The internal VCC and VREF regulators continue to operate when the line UVLO pin is below threshold. The LM5025A PWM controller contains all of the features necessary to implement power converters utilizing the Active Clamp / Reset technique. With the active clamp technique, higher efficiencies and greater power densities can be realized pared to conventional catch winding or RDC clamp / reset techniques. Two control outputs are provided, the main power switch control (OUT_A) and the active clamp switch control (OUT_B). The two internal pound gate drivers parallel both MOS and Bipolar devices, providing superior gate drive characteristics. This controller is designed for high-speed operation including an oscillator frequency range up to 1MHz and total PWM and current sense propagation delays less than 100ns. The LM5025A includes a high-voltage start-up regulator that operates over a wide input range of 13V to 90V. Additional features include: Line Under Voltage Lockout (UVLO), softstart, oscillator UP/ DOWN sync capability, precision reference and thermal shutdown. Features n Internal Start-up Bias Regulator n 3A pound Main Gate Driver n Programmable Line Under-Voltage Lockout (UVLO) with Adjustable Hysteresis n Voltage Mode Control with Feed-Forward n Adjustable Dual Mode Over-Current Protection n Programmable Overlap or Deadtime between the Main and Active Clamp Outputs n Volt x Second Clamp n Programmable Soft-start n Leading Edge Blanking n Single Resistor Programmable Oscillator n Oscillator UP / DOWN Sync Capability n Precision 5V Reference n Thermal Shutdown Packages n TSSOP-16 n LLP-16 (5x5 mm) Thermally Enhanced Typical Application...