LP3929 Datasheet | National Semiconductor

Description The LP3929 is designed for portable and wireless applications requiring level translation and power supply generation in a pact footprint. The device level translates 1.8 V LVCMOS on the host (A) side to 2.85 V LVCMOS levels on the card (B) side for a mini SD / SD 4-bit bi-directional data bus. Independent direct control of the CMD, Data0 and Data1-3 paths support mini SD state machine requirements. A shutdown pin is provided for the level shifters and regulator. The f_CLK_A is a feedback clock to the host which can be used to overe level shifter bus delay. The built-in low-dropout voltage regulator is ideal for mobile phone and battery powered wireless applications. It provides up to 200 m A from a 3.05 V to 5.5 V input. It is stable with small 1.0 µF ± 30% ceramic and high quality tantalum output capacitors, requiring smallest possible PC board area. The card (B port) side channels have integration of ASIP (Application Specific Integrated Passives) - on chip integrated pull-up, pull-down, series resistors and capacitors for EMC filtering. It is designed to tolerate IEC61000-4-2 level 4 ESD: ± 15 k V air discharge, ± 8 k V direct contact. Key Specifications Level Shifter: n 6-signal Level Shifter (5 bi-directional and 1 uni-direction) n 3 ns (typ) propagation delay n Channel-to-channel skew < 1 ns (max) Low-Dropout Regulator: n 3.05 V to 5.5 V input range n 2.85 V at 200 m A n Fast Turn-On time: 30 µs (typ) n 110 m V (max) dropout with 200 m A load n Thermal shutdown at 160˚C (typ) Protection Block (B Side): n Robust IEC ESD Protection: ± 15 k V Air Gap, ± 8 k V Direct Contact n ASIP / EMI Filtering Features n Ultra small micro SMD 24 bump package n 6-signal level translation 1.8 V to 2.85 V n LDO stable with ceramic and high quality tantalum capacitors Typical Application Circuit © 2006 National Semiconductor Corporation DS201868 .national. Block Diagram .national. Package Outline and Connection...