LP3996 Datasheet | National Semiconductor

Description The LP3996 is a dual low dropout regulator with power-onreset circuit. The first regulator can source 150m A, while the second is capable of sourcing 300m A and has a power-onreset function included. The LP3996 provides 1.5% accuracy requiring an ultra low quiescent current of 35µA. Separate enable pins allow each output of the LP3996 to be shut down, drawing virtually zero current. The LP3996 is designed to be stable with small footprint ceramic capacitors down to 1µF. An external capacitor may be used to set the POR delay time as required. The LP3996 is available in fixed output voltages and es in a 10 pin, 3mm x 3mm, LLP package. . Key Specifications n n n n Input Voltage Range Low Dropout Voltage Ultra-Low IQ (enabled) Virtually Zero IQ (disabled) 2.0V to 6.0V 210m V at 300m A 35µA < 10n A Package All available in Lead Free option. 10 pin LLP 3mm x 3mm For other package options contact your NSC sales office. Applications n Cellular Handsets n PDA’s n Wireless Network Adaptors Features n 2 LDO Outputs with Independent Enable n 1.5% Accuracy at Room Temperature, 3% over Temperature n Power-On-Reset Function with Adjustable Delay n Thermal Shutdown Protection n Stable with Ceramic Capacitors Typical Application Circuit © 2006 National Semiconductor Corporation DS201458 .national. .. Functional Block Diagram Pin Descriptions LLP-10 Package Pin No 1 2 3 4 Symbol VIN EN1 EN2 CBYP Name and Function Voltage Supply Input. Connect a 1µF capacitor between this pin and GND. Enable Input to Regulator 1. Active high input. High = On. Low = OFF. Enable Input to Regulator 2. Active high input. High = On. Low = OFF. Internal Voltage Reference Bypass. Connect a 10n F capacitor from this pin to GND to reduce output noise and improve line transient and PSRR. This pin may be left open. Set Delay Input. Connect a capacitor between this pin and GND to set the POR delay time. If left open, there will be no delay. mon Ground pin. Connect...