TP11362 Datasheet | National Semiconductor

Description The TP11362A is a quad (4) channel Adaptive Differential Pulse Code Modulation (ADPCM) transcoder, fully patible to ITU G.726 remendation in 40 kbps, 32 kbps, 24 kbps, 16 kbps and ANSI 32 kbps modes. The TP11362A ADPCM processor can operate on up to 8 independent channels in an 8 k Hz frame. Each channel is individually configured, supporting both full and half duplex operation. All input/output transfers occur on an interrupt basis using serial, double buffered data registers. Together with National’s TP3054/57 BO ® or TP3070/71 BO II devices, the TP11362A forms plete ADPCM channels with Codec/ filtering. Features n CCITT G.726 patible at 40, 32, 24, 16 kbps n ANSI T1.301 patible at 32 kbps n 8-channel half-duplex (encode or decode) or 4-channel full-duplex operation in 8 k Hz frame n Each channel individually configurable n Selectable µ-law or A-law PCM coding n Asynchronous 8 MHz master clock operation n TTL and CMOS patible inputs and outputs n 28-pin PLCC or 24-pin DIP packages n Power consumption of typ. 6 m W at +5V per full-duplex channel n On-Chip Power-On-Reset n - 40˚C to +85˚C operating temperature range n Single 5V supply Block Diagram DS012877-1 FIGURE 1. Block Diagram TRI-STATE ® and BO ® are registered trademarks of National Semiconductor Corporation. © 1997 National Semiconductor Corporation DS012877 .national. Connection Diagrams Plastic Chip Carriers Plastic Dual-In-Line DS012877-2 DS012877-3 Top View Order Number TP11362AV See NS Package Number V28A Top View Order Number TP11362AN See NS Package Number N24A CLK Master clock input. CLK may be asynchronous to PSCK or ASCK. CE Chip enable input. When CE is high, it enables data transfer. The falling edge of CE latches and transfers the serial data TSI or RSI to the core for processing and strobes the control signals QSEL0, QSEL1, PCM1, EN and INIT. CE should change state only when PSCK and ASCK are high. CE, when low, sets the TSO and RSO outputs into TRI-STATE mode. TRB...