TP5510 Datasheet | National Semiconductor

Description The TP5510 consists of a m-law monolithic AFE device utilizing the A D and D A conversion architecture shown in Figure 1 and a serial data interface The device is fabricated using National’s advanced double-poly CMOS process (micro CMOS) The A D portion of the device consists of an input gain adjust amplifier an active RC pre-filter which eliminates very high frequency noise and a switched-capacitor band-pass filter that rejects signals below 200 Hz and above 3400 Hz Also included are auto-zero circuitry and a pressing A D which samples the filtered signal and converts it to the m-law digital format The decode portion of the device consists of an expanding D A which reconstructs the analog signal from the pressed m-law code a low-pass filter which corrects for the sin x x response of the D A output and rejects signals above 3400 Hz followed by a singleended power amplifier capable of driving low impedance loads The device requires a 1 536 MHz 1 544 MHz or 2 048 MHz master clock bit clocks which may vary from 64 k Hz to 2 048 MHz and 8 k Hz frame sync pulses Features Y Y Y Y Y Y Y Y Y Y Y Y plete A D and D A with filter system including Serial Data Interface Encode high-pass and low-pass filter Decode low-pass filter with sin x x correction Active RC noise filters m-law patible A D and D A Internal precision voltage reference Internal auto-zero circuitry m-law TP5510 g 5V operation Low operating power typically 60 m W Power-down standby mode typically 3 m W Automatic power-down TTL or CMOS patible digital interfaces Maximizes PC card circuit density Plastic DIP and SOIC packages 8-bit digital I O 13-bit dynamic range Use with DSP processor Applications Tapeless Answering Machines Cordless Phones Cellular Radio Connection Diagram Dual-In-Line Package TL H 11186 - 1 Top View Order Number TP5510WM See NS Package Number M16B Order Number TP5510N See NS Package Number N16A TRI-STATE is a registered trademark of National Semiconductor Corporation C1996...