NVP6124B
Description
NOTE 2015-10-20 2016-02-23 2017-03-14 - Initial Draft - Pin Description Change : Pin 9, 10, 11, 12, 27 GND => NC Page 8 - OUTPUT PORT Description Change (1) BANK1 0xC0~C3(VPORT_1 VPORT_2) (2) BANK1 0xC8/C9 (CH_OUT_SEL_1 CH_OUT_SEL_2) (3) BANK1 0xCA[7:4] (VCLK_1_EN VCLK_2_EN) Page 54~55 (4) BANK1 0xCA[3:0] (VDO_1_EN VDO_2_EN) Page 111~112 (5) BANK1 0xCD[7:4]/CF[7:4] (VCLK_1_SEL VCLK_2_SEL) (6) BANK1 0xCD[3:0]/CF[3:0] (VCLK_1_DLY_SEL VCLK_2_DLY_SEL) (7) BANK1 0xD2 (VDO_INV_1 VDO_INV_2) - Power Supply Current Modified Page 127 ☞ Contact Information Homepage : .nextchip.
