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NIKO-SEM
N-Channel Logic Level Enhancement Mode Field Effect Transistor
P50N03LDG
TO-252 (DPAK) Lead-Free
D
PRODUCT SUMMARY V(BR)DSS 27 RDS(ON) 12m ID 50A 1. GATE 2. DRAIN 3. SOURCE
G S
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Avalanche Current Avalanche Energy Repetitive Avalanche Energy Power Dissipation
2 1
SYMBOL VGS
LIMITS ±20 50 35 150 33 250 8.6 50 30 -55 to 150 275
UNITS V
TC = 25 °C TC = 100 °C
ID IDM IAR
A
L = 0.1mH L = 0.05mH TC = 25 °C TC = 100 °C
EAS EAR PD Tj, Tstg TL
mJ
W
Operating Junction & Storage Temperature Range Lead Temperature ( /16” from case for 10 sec.
P50N03LDG Datasheet
