Datasheet4U Logo Datasheet4U.com

SM5852CS - Dynamic Range Compression LSI

General Description

Number 1 2 3 4 5 6 7 8 9 10 11 12 13 Name LRCI BCKI DI CLK VSS RSTN TESTN MUTEN DOUT BCKO LRCO VDD OPT I/O1 Ip Ip Ip I Ip Ip Ip O O O

Ip Input data sample rate (fs) clock input Bit clock input Serial data input Clock input Ground System reset initialization.

Reset when LOW.

Key Features

  • s s s s s s s s s s s s 2-channel processing 6 input-level dependent dynamic gain characteristics Dynamic range compression bypass mode 2 attack time settings Soft muting function Serial input/output interface 2s complement, MSB first, 16-bit 384fs system clock 23 × 23-bit multiplier/30-bit high-precision accumulator TTL-compatible input/output 3.2 to 5.5 V operating voltage range 16-pin SOP Molybdenum-gate CMOS.

📥 Download Datasheet

Datasheet Details

Part number SM5852CS
Manufacturer Nippon Precision Circuits Inc
File Size 132.88 KB
Description Dynamic Range Compression LSI
Datasheet download datasheet SM5852CS Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SM5852CS NIPPON PRECISION CIRCUITS INC. Dynamic Range Compression LSI OVERVIEW The SM5852CS is a digital signal processor IC that performs dynamic range compression for use in digital audio reproduction equipment. It is designed for use with a 44.1 kHz sampling frequency. PINOUT LRCI BCKI DI CLK VSS RSTN TESTN MUTEN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 DB/DS MOD2 MOD1 OPT VDD LRCO BCKO DOUT SM5852CS FEATURES s s s s s s s s s s s s 2-channel processing 6 input-level dependent dynamic gain characteristics Dynamic range compression bypass mode 2 attack time settings Soft muting function Serial input/output interface 2s complement, MSB first, 16-bit 384fs system clock 23 × 23-bit multiplier/30-bit high-precision accumulator TTL-compatible input/output 3.2 to 5.